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I tried running SweRV with Mentor Graphics's Questa simulator. I see testbench/flist.questa file-list, but Makefile didn't have targets for the same. I added the same and then found few minor issues i…
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Hi,
If there is an 8-byte access, the sbaddress will not auto increment. A mistake in code means that the address will be incremented by 8 if it's a 16-Byte access (illegal)
dbg.sv:272
`({4{(…
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Would it make sense to combine [prim_util.svh](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim/rtl/prim_util.svh) with [prim_assert.sv](https://github.com/lowRISC/opentitan/blob/master/hw/…
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Hello,
I have a design with a non-rectangular standard-cell area (The initial DEF has several macros placed and the std cells rows do no overlap with the macros) - It crashes with a free() invalid…
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Currently, the Riviera backend calls `vlog` for each Verilog file individually, which results in each file being a separate compilation unit. This behavior is inconsistent with other tools supported b…
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I am trying to use verilator on the .sv (or .v) output from Clash, the high level HDL. Clash has successfully generated netlists and .sv files in Test/TestBench/ but when I run verilator .. -ITest/Te…
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Hi , if we want to use the iccm ,Can I simply edit the link file, And let the cpu core to automatically download the code from external rom/ram/flash, is that possible, if we do not have the dma maste…
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Hello,
I am just trying to run swerv design on xilinx zed board using vivado and instead of running it in the debug mode using jtag and uart, i want to interface this with zedboard io's.
Could you…
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I get an error during the synthesis of the swerv fpga SoC. It seems some dependencies are not found.
[VivadoError.txt](https://github.com/westerndigitalcorporation/swerv_eh1_fpga/files/3809732/Viva…
EyssK updated
4 years ago
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Dear
I am using the NRF52832, using the following prj
```
##########
# for GPIO
##########
CONFIG_GPIO=y
##########
# for BLE
##########
CONFIG_BT=y
CONFIG_SENSOR=y
##########
# f…