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Xyce is a new spice-compatible simulation kernel. It provides circuits simulation using parallel computations (via openMPI ). More info about Xyce at http://xyce.sandia.gov/. The purpose of QucsXyce i…
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There may be way to overcome #34 and #41.
I started implementation of `spice4qucs` extension. This extension allows you to switch between `qucsator` simulation kernel and `ngspice` simulation kernel.…
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I am working in a personal project in a university hosted server using Red Hat 4.4.
It has Python 2.6.6 installed because the repositories are old for RH4.4 .
I compiled and installed (locally) Pyth…
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An issue that keeps coming up in various guises, and is the root cause of [this PR](https://github.com/jandecaluwe/myhdl/pull/67), is the problem of global state in simulation instances.
It has been …
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When I'm running ..vsim/vcompile/rtl/vcompile_tb.sh using Modelsim SE-64 10.0b
I get a error in the following line:
`vlog -quiet -64 -work ${LIB_PATH} -ccflags "-I${TB_PATH}/mem_dpi/" …
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we should put them into a (non-free) extension package.
we need to implement a way to make use of such an extension.
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The VUnit Python runner currently support Modelsim but it's designed to support multiple simulators. What other simulators would you like to see supported? Let's have some voting.
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Hello,
is it planned to bring AMS support to GHDL?
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Author Name: **Felix Bors** (@felixbors)
Original Redmine Message: 1910 from https://www.veripool.org
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I am trying to compile a small Verilog module into a dynamic object
(ex Verilog -> …
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I'm using ghdl with VHPI to setup co-simulations. In the 'external' part
stdout is either set to autoflush (e.g. in perl), or a flush is done after
each message (e.g. in C/C++).
In my test environmen…