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Dear
I am using the NRF52832, using the following prj
```
##########
# for GPIO
##########
CONFIG_GPIO=y
##########
# for BLE
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CONFIG_BT=y
CONFIG_SENSOR=y
##########
# f…
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hi,
when I execute the command
fusesoc run --target=sim swervolf
the following error met,
INFO: Generating ::swervolf-swerv_default_config:0
Traceback (most recent call last):
File "/home/…
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@aprnath ,
I am trying to use a DCCM without multiple bank access capability. The current DCCM (say DCCM_orig) interface looks like this
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output logic dccm_…
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Are there any plans to support SV dynamic types?
support of SV queues and associative arrays would be very appreciated. ( at least of basic types and structures of basic types ).
Need something …
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I'm playing with `civetweb` webserver module on latest zephyr tree and I see some issues here
## stack size
When I try to serve a bit bigger pages that are in provided in samples I got stack overf…
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It is ok for verilator.
but if I want to use VCS, fusesoc run --target=sim --tool=vcs --run swervolf --ram_init_file=../cores/Cores-SweRVolf/sw/zephyr_hello.vh
It seems the zephyr did not load …
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Hi
I ran entire swerv design using nangate 45nm, which has a post-synth instance count of about 140k...Runs extremely well.....Kudos to entire team
2 things I found missing was
1) PG mesh - Is …
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Hi there, I wanted a way to disassemble instructions to their symbolic names and as per the Readme, it is possible through the --disass param for whisper. However, it doesn't seem to be there.
Is t…
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Hi,
I tried building it on a 32-bit Ubuntu machines with 1.67 boost libs and gcc 7.4
After fixing the initial errors in ```Core.cpp``` related to the usage of ```__uint128_t``` datatypes, I was…
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As part of packaging the SweRV EH1 core, I'm trying to figure out what would be the correct VLNV identifier. For those unaware of VLNV, it's an classification system for IP cores, stemming from the IP…
olofk updated
5 years ago