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Hello, thank you very much sharing your valuable materials. I have some experience using Vivado HLS but I am still a slow learner for Hardware/FPGA design.
I am trying to run these Verilog files wi…
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Hey,
My self and a number of server owners as you know use R3F 3.1 and i for one would certainly use your heavily modified version of R3F_ARTY_AND_LOG if it wasn't for one key feature that's missing…
ghost updated
8 years ago
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OS system : Ubuntu 22.04 ( Vivado v2024.1 64-bit )
project release : commit cdca76bbeebe8ea02333fd41829ffdf69d21a03c ( Linux kernel 6.9.6 )
project build : make CONFIG=rocket64b1 BOARD=arty-a7-100t…
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Hi, I'm trying to make some predictions in the mini dataset described in the [Artic readme](https://github.com/zc-alexfan/arctic/blob/master/docs/data/README.md) using the checkpoint disponibilized, b…
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Hi,
I am currently trying to access the 256MB of off-chip memory (DDR) on the arty-35T.
I first started to play with the available configurations (i.e., `TinyConfig` in `rocket-chip/src/main/scala…
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### Game or games this happens in
UCES-01250
### What area of the game
*
### Speed seen in PPSSPP
60% (20/30)
### GE frame capture and debug statistics
[UCES01250.ppdmp.zip](https…
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Command: ./make.py --board=arty_a7 --cpu-count=1 --toolchain=symbiflow --build
* I did remove the extra xadc for the arty in the make.py line 92
Error:
```
Executing module `synthesize`:
[1…
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Hello,
I understand that Arty A7 is supported, I want to confirm if Arty S7 need something extra to work.
I follow the build instructions and when loading the gateware on Arty S7 I am getting the …
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The array which gets a list of vehicles to add just takes a list of classnames. This means if an opfor arty spawns, and it is in the arty support module list, players can call opfor artillery.
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**What needs to be done:**
**Suggestions on how to get it done:**
**What are the arguments for getting it done:**
**Task is considered finished when:**