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@acomodi @kgugala I have been testing the symbiflow tool chain with designs from several FPGA websites and have encountered a rather perplexing bug within the toolchain. While working on the [Ad Astra…
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While compile the project mentioned in [the problem](https://github.com/ghdl/ghdl/issues/1307) and happened errors! What's wrong with this?
command as mentioned in the above problem :
`yosys -m ghdl…
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When running Symbliflow on the attached design, I am getting the following error:
# Building complex block graph took 0.04 seconds (max_rss 25.9 MiB, delta_rss +13.1 MiB)
Error 1:
Type: Blif fil…
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Generating bitstream by following the steps mentioned in this Makefile: https://github.com/Talha-Ahmed-1/picofoxy/blob/main/fpga/Makefile
It got stuck at the time of synthesis and giving such error…
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I'm instantiating the macro for clock and it fails packing. This is my Verilog:
```verilog
qlal4s3b_cell_macro u_qlal4s3b_cell_macro (
.Clk_C16 (clko),
.Clk_C16_Rst (),
.Clk_C21 …
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Hi, I'm following the doc on https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html and the first 2 examples work fine, but litetx is not as clear.
First "Linux LiteX demo" does…
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With the assumption of .route file store the pips's names how to convert f4pag's result into dcp file and generate bit through vivado?
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Issue from https://github.com/SymbiFlow/vtr-verilog-to-routing/issues/524.
Alias are not considered when processing the `get_clocks` call when doing min/max delay constrainsts in the SDC.
#### Exp…
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@acomodi @vaughnbetz @tangxifan I am attempting to run the VTR SymbiFlow (f4pga) benchmarks with the 100t and 200t devices. Currently, I am able to run the benchmarks with the 50t device. I have inclu…
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While testing the [RR graph base costs fixes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1576) I came across a possible instability issue that causes run-time and QoR to drastic…