-
According to https://github.com/f4pga/prjxray/issues/1384, this repo holds a standalone implementation of fasm2frames. However, prjxray still ships a copy of fasm2frames, e.g. at https://github.com/f4…
-
Currently building anything with the snap package will result in the following warning.
```
/snap/openxc7/current/usr/lib/python3/dist-packages/fasm/parser/__init__.py:30: RuntimeWarning: Unable …
-
There is a `synth_quicklogic` pass in [yosys: techlibs/quicklogic](https://github.com/YosysHQ/yosys/blob/master/techlibs/quicklogic/synth_quicklogic.cc) as well as in [yosys-f4pga-plugins: ql-qlf](ht…
-
It would be super nice to have a tutorial that can walk users through:
1. Setting up F4PGA and generating a bitstream
2. Copying it to the Pi and blinking an LED
3. Modify the design to use a UAR…
-
It would be great to support the open source FPGA tooling from https://f4pga.org/ project. Examples on how to use the tooling for Xilinx 7 series parts can be found here -> https://f4pga-examples.read…
-
This issue is a reminder to regularly review code and
- push tested code to upstream projects where possible.
- separate i) system requirements (readily available from upstream), ii) customization …
-
All the headers should have ids so that you can link directly to it. For example the "Current status" section.
-
The last step of the installation is to install a set of tar files like this:
```
mkdir -p $INSTALL_DIR/xc7/install
wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-…
-
In my core, I use Symbiflow tool to synthesize and generate bitstream to an Artix 7 FPGA.
I recently needed to pass a vlogdefine to Yosys due to memory initialization but the parameter is not passe…
-
From https://github.com/chipsalliance/f4pga-examples/issues/277#issuecomment-1077533522
-----
> First of all it looks like you are using an outdated Yosys version (`Yosys 0.9+4270 git sha1 539d4ee9`…