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I've done some tests with liveness proofs using PSL properties like:
```vhdl
assert always (rose(a) -> eventually! b);
```
I noticed that such constructs are processed by GHDL (and Yosys), but…
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Coming from tgingold/ghdlsynth-beta#74
Ref #1458
> To avoid specifying `-m ghdl` when calling yosys, it would suffice if yosys looked at the plugins available in its own plugins directory.
>
> …
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Using Yosys and Yosys GHDL plugin, from this instantiation:
> FF_0: FD1P3DX
> port map (D=>RdAddress(10), SP=>RdClockEn, CK=>RdClock,
> CD=>'0', Q=>raddr10_ff);
I get the …
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While building the plugin via "make", I was getting the following error.
```
src/ghdl.cc:760:8: error: use of undeclared identifier 'Id_Dlatch'; did you mean 'Id_Latch'?
case Id…
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```yaml
ref: https://www.linkedin.com/posts/rodrigoalejandromelo_fpga-activity-6720313853093130240-MeQH/
tags:
- lattice
- ice40
- vhdl
- components
- synthesis
- ghdl-yosys-plugin…
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@tmeissner has a repository for testing GHDL's PSL capabilities.
Maybe this should be integrated too.
https://github.com/tmeissner/psl_with_ghdl/
-----------------
/cc @umarcor
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Yesterday, Yosys was added to MSYS2's MINGW-packages repository. As seen in the PKGBUILD recipe (https://github.com/msys2/MINGW-packages/blob/master/mingw-w64-yosys/PKGBUILD), it depends on GHDL and g…
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Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …
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Hi,
I face the very same issue as https://github.com/antmicro/yosys-systemverilog/issues/1776.
How did you solve it? Is it just a matter of updating glibc? I am using a dockerized version of open…
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Tasks:
- [ ] Move all of the Lakeroad-related stuff onto its own branch
- [ ] Make Lakeroad stuff build optionally; connect it to an external Lakeroad with the Yosys plugin system
- [ ] Clean up …