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The integration code in LiteXSoC is tightly coupled to the cores and we should move the code related to LiteDRAM/LiteEth/LiteSDCard/LiteSATA directly to the respective repositories. This would ease ad…
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Hi there,
I'm using your CPU in a quad core constellation on a nexys video. The SoC was generated with:
```
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard…
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I've been banging my head against this for two days now. Reaching out in the hopes of some guidance/pointers. 🙇
I am using a ULXS3 board and have connected two LAN8720 PHY modules via RMII. So far…
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TODO.
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I have this test design for GTP transceivers, which contains
a counter and LEDs driven by the TX clock.
Unfortunately with this kind of writing the migen code:
https://github.com/openXC7/primitive-…
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The README file mentions the following:
```
3. Check out /examples/versa_ecp5_udp_loopback for a good practical example of how to get
started with the Liteeth core solo in an FPGA.
```
I've t…
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# Bug Report
## One-Line Summary
In some configurations Vivado fails to build gateware.
## Issue Details
### Configuration
```json
{
"target": "kasli",
"min_artiq_version": "…
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Litex appears to consider iospace to be 0x80000000 and above when configuring a vexriscv cpu.
Unfortunately this is only true sometimes:
https://github.com/litex-hub/pythondata-cpu-vexriscv/blob…
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https://libera.irclog.whitequark.org/litex/2021-10-20#31037395;
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Is there a way to do mdio writes when the core is configured in udp mode?
Here's my core config:
```
# PHY ----------------------------------------------------------------------
phy: Lit…