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On the ULX3S we have 'slow' USB 1.1 host. With this PMOD it should be possible to have USB2.0 at 480Mbit/s
Are there any examples for this USB board? Can the ULPI be used as a replacement PHY in othe…
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I am using below example for pysnmp. Sometimes it works well but sometimes it stops midway and gives timeout error.
```
from pysnmp.carrier.asyncore.dispatch import AsyncoreDispatcher
from pysnmp.c…
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Hello, I installed Vivado 2020.2 on a new machine, and tried to get the PMOD AD5 working by following [these instructions](https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips…
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Hi,
I am adding support for the 'Tang Primer 25k' and am trying to get the bundling working to make it easier to test, but am not having much luck. Could you please document the bundling process.…
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As you’ve hard wired some of the outputs to be inputs - mentioned in #6 - do you need to have a template in the firmware to stop the FPGA trying to output on those lines? Presumably, you need to repla…
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### Issue Type
Usability
### HEU Version
newest
### OS Platform and Distribution
Ubuntu 22.04
### Python Version
3.10
### Compiler Version
gcc 14.2
### Current Behavior?
In heu/library/alg…
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For testing our application, [Loadouts for Genshin Impact](https://github.com/gridhead/gi-loadouts), we see a very high memory usage of up to 4.0 GiB even when the actual run of the application takes …
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There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
3 months ago
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if nothing else, adding the image below to the 'img' directory and the Readme will help. time to start the Wiki?
![icebreaker_png_project-body](https://user-images.githubusercontent.com/6507573/62404…
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Hi,
I am trying to understand the API, and I have encountered something that seems to be either a bug or unintended behaviour. (ZCU216, latest distribution)
```
from qick import QickSoc
from qic…