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I'm on the current `sycl/unified/next` branch and using Vitis 2020.2 with a `xilinx_u200_xdma_201830_2` target. Compiling the `single_task_vector_add` test case works fine but it fails once `vpl` is c…
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So far we have 2 working modes -- one for LHC trigger (low reuse factor, 1-6, weights in the fabric) and one for "naive" serial mode (see PR #45).
One interesting mode is a very large reuse facto…
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Reduce the number of pointers
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This is a reminder to come back to this issue:
`test-histogram` works fine with real hardware on an `f1` AWS instance, but `bench-histogram` does not:
(taken from the [example in this repository…
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Hi,
We have just received access to the U280 board (no aws), we would like to test/extend the hls4ml code for this board, however I am afraid we can't find a complete developer documentation with g…
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Take this perf analysis, for example, recorded while an synthesis is happening with vivado:
```
sudo yum install -y perf
sudo perf record -g -a sleep 10
sudo perf report
```
```
[snip]
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make -C pkgs
make[1]: Entering directory '/home/enai/Desktop/project/heterocl/pkgs'
/bin/sh: 1: /home/enai/Desktop/project/heterocl: Permission denied
make[2]: Entering directory '/home/enai/Deskto…
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Hello, I try to use python to run the Alexnet model,My code like this:
```
import caffe
MODEL_FILE = 'alexnet_four_channel_model.caffemodel'
DEPLOY_FILE = 'config/deploy.prototxt'
TEST_ROOT =…