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![Uploading 0fdd12cd-e038-4a25-b084-1f83504b4812.png…]()
Hi, recently I have been using your nax gen.scala file to generate a core with three axi interfaces, ibus,dbus,pbus, After connecting anothe…
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I am working on pure-C implementation for OpenVizsla host software: https://github.com/matwey/libopenvizsla
I've faced the following issue with FPGA firmware last summer.
I have been not able to mak…
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Does anyone have a working SDRAM controller example for the ESMT devices used on V7 hardware? I quickly looked at the 3'rd party LiteX i the repos but it seems like an uncertain way to start there.
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Hi zangman:
This is an awesome project and wiki! I appreciate your detailed instruction. I wonder whether there is a reversing version of using SDRAM like FPGA directly write the data to SDRAM on H…
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stm32 208 meets x16 SDRAM
[0900766b815247be.pdf](https://github.com/rusefi/rusefi-hardware/files/7836950/0900766b815247be.pdf)
[STM32F429BIT6-College-shop-Store-Circuit.pdf](https://github.com/r…
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Hello! I was working in the FPGA - SDRAM Communication project. All was going fine up to the part of the U-boot programming.
In instruction # 4:
"""
Now we load the rbf file into memory and then …
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Hi
I recently contact JLCPCB service to produce PCBs for SDRAM XSD v2.5. I used this gerber file: https://github.com/MiSTer-devel/Hardware_MiSTer/blob/master/releases/sdram_xsd_2.5.zip
Unfortuna…
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Hi, I am looking for that controller in Verilog/system Verilog. Can you help me please?
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Hi,
initially, thank you for the great APP and your commitment by developing.
I have connected my D300s and the Nexus7(2012) with a USB cable.
I set the recording media to "SDRAM" the path is d…
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```
Hi,
initially, thank you for the great APP and your commitment by developing.
I have connected my D300s and the Nexus7(2012) with a USB cable.
I set the recording media to "SDRAM" the path is d…