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The following are closely related:
- SoC design, peripheral integration
- processor reference manual
- device drivers
- platform init / boot flow
Given a [declarative language for modeling an…
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## Current Behaviour
From the user guide, it states that duplicate names are not allowed:
![image.png](https://raw.githubusercontent.com/tituschewxj/pe/main/files/2918b01c-8d9f-45a4-b08c-7373dad4391…
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This is a meta issue trying to collect use-cases related to Zephyr multi-image builds.
Building of multiple images through a single build invocation together with flashing capabilities is a recurri…
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@cerna
https://github.com/machinekit/mksocfpga/pull/115/checks?check_run_id=1294764215
AFAIK someone pulled the plug on the old build system a while ago and
someone is yet to place in the replac…
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Hello.
I have been using LibSystemCTLM-SoC to cosimulate my Zynq designs for behavioral/RTL simulations.
I use generated simulation scripts and files from Vivado and replace the "processing_syst…
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Hi All:
May not be an issue, but would like to confirm if the following are concerned errors for Xilinx vivado gateware creation.
Gateware build was successful, but wanted to confirm before writing…
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I'm trying to simulate it with Xcellium and getting whole design in Xs after first access to DCCM.
It seems to me that the memories moved to TB are not connected/wrongly connected to design:
…
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There seems to be a missing dependency causing randsoc_dump to fail sometimes.
This will create `design_0/design.tcl`:
```
build /home/jgoeders/bfasst/build/rand_soc/design_0/design.tcl: rand_soc…
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Currently, the `StorageScheduler` is saving the power flows of the storage but not the state of charge. Even though there is a direct relation, it's not trivial as we could have different charging / d…