-
```
ModelSim reports missing libraries when running FPCIe example.
# ** Error: (vsim-19) Failed to access library 'secureip' at "secureip".
#
# No such file or directory. (errno = ENOENT)
# ** Erro…
-
```
ModelSim reports missing libraries when running FPCIe example.
# ** Error: (vsim-19) Failed to access library 'secureip' at "secureip".
#
# No such file or directory. (errno = ENOENT)
# ** Erro…
-
One of the basic ideas of QNICE-FPGA is, that it is meant to be highly portable. For sure we are not there, yet ;-)
Currently, everything is quite Xilinx specific.
* Right now, we have two hardw…
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Hi !
I am using a Cypress PSoC board (https://www.cypress.com/documentation/development-kitsboards/cy8ckit-059-psoc-5lp-prototyping-kit-onboard-programmer-and) but I often simulate my circuits on Log…
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While trying to synthesize the cpu16 project, all my toolchains (xilinx ISE and yosys) choke on this:
```
assign IP = cpu.regs[7];
assign zero = cpu.zero;
assign carry = cpu.carry;
assi…
-
Hi.
I'm very newbie in hardware design system and i'm trying to build `XRT` in docker for `pynq` system also installed via `pip3`, without any Vitis, Vivado or ISE. just for connecting pynq to XRT to…
-
```
ModelSim reports missing libraries when running FPCIe example.
# ** Error: (vsim-19) Failed to access library 'secureip' at "secureip".
#
# No such file or directory. (errno = ENOENT)
# ** Erro…
-
Hello, sorry for using your github issues page as my newbie training ground, but I am enjoying building the accelerator and I finally got the xilinx working and recognized in ISE. I have yet to acquir…
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Hi,
I am really new to the FPGA stuff and tried to setup a project using OR1200.
I like to start with my board from XESS:
http://www.xess.com/shop/product/xula2-lx25/
https://github.com/xesscorp/XuL…
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Hi, I'm writing a IDE for GHDL & GTKWAVE with additional features (automatically generated testbench, automatically generated declare and instance for components, etc) what do you think?
https://www.…