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Hi,
Firstly thank you very much for this tremendous effort and I wish you all the best.
I am trying to install the prebuilt toolchain you made and when I test it in one of the provided examples (bli…
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The FPGA implementation part of the Windows workflow keeps failing (cut-out from https://github.com/stnolting/neorv32/runs/3562298603?check_suite_focus=true#step:5:27).
```
yosys -m ghdl.so \
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The external Instruction memory (a) should check for the it valid cycle signal not for the b external memory signal:
https://github.com/stnolting/neorv32/blob/3be750c5e286aca58ae488a78dbecb9ade1052…
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[workflows/sphinx-tuttest.yml](https://github.com/SymbiFlow/symbiflow-examples/blob/master/.github/workflows/sphinx-tuttest.yml) currently requires the addition of each new design to the CI matrix for…
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Hello!
First of all, thanks for sharing this great project.
I'm new to vhdl, tested the project with an altera ep4ce6 and it worked, then I decided to put it into real operation on a hardware with X…
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**Description**
Latches are usually not what you want in your design, but sometimes they are necessary afterall. Currently, ghdl crashes when trying to synthesize one.
**Expected behaviour**
GHDL…
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I have gotten as far as checking the Toolchain and Info by make check and make info in /sw/example/blink_led. But all other examples end up with the error message above. I am trying to set up neorv32…
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This is a bug we found while testing the DOM with NEORV32. Precisely, with file https://github.com/stnolting/neorv32/blob/master/rtl/templates/system/neorv32_SystemTop_axi4lite.vhd. By changing https:…
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I have some doubts regarding the current concept of the processor wrapper, i.e. [`rtl/templates/processor`](https://github.com/stnolting/neorv32/tree/master/rtl/templates) and [`rtl/templates/system`]…
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Hello,
I've been trying to run some software examples on a Fomu.im board. After some experimenting i realized that the neorv32_uart_print() outputs were missing. After some debugging i realized tha…