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I've run
sauron:~/fpga/CFU-Playground$ ./scripts/setup
and it worked fine.
Then
```
sauron:~/fpga/CFU-Playground/proj/proj_template$ make prog
(...)
INFO:SoC:IRQ Handler (up to 32 Locations)…
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The CC debugger (which controls the spy port) doesn't currently work. Getting this to work will likely be critical to getting the UHDL to boot on the Arty A7 and for future work.
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After running the following lines I could not boot the Arty A7:
```
python3 ./arty.py --toolchain vivado --cpu-type vexriscv_smp --sys-clk-freq 100e6 --with-etherbone --csr-csv csr.csv --load
pyt…
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I run the commands to clone the repository and start building but failed.
`$ make -f Makefile.x300artydevkit mcs`
`make -C /home/a/mf/multizone-fpga/rocket-chip/firrtl SBT="java -jar /home/a/mf/mult…
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Dear developers,
in your README you mention _Currently, only the Arty-A7 (xc7a35t) FPGA board is supported (TARGET=arty)_ but at the same time also have a section about the _ZCU104 board_. Can I as…
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## My Environment
**EDA tool and version:**
**Operating system:**
**Version of the Ibex source code:**
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I updated LiteX and RISCV tools and managed to run Linux on LiteX VexRiscV on Arty_A7 with 4 cores, which was quite impressive, thank you!
Now, to run bare metal apps, I tried compiling the demo but …
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I'm attempting to build for an Arty A7 100T and it doesn't seem the `--device` argument doesn't seem to be working, as it's still selecting the 35T part.
```
$ ./make.py --board=arty --device=xc7a…
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Dear developers,
I'm totally new in this hardware world, so sorry if these questions might look obvious to you. I'm wondering how exactly we can use this DRAM controller implementation in our resea…
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```
$ ./litex_boards/targets/arty.py --cpu-type microwatt --cpu-variant standard+irq --integrated-rom-size=$((48 * 1024)) --build --variant a7-100 --with-ethernet
INFO:SoC: __ _ __ _ …