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**Bug description**
On Arty-7 board when running the eth dumb_http_server with vexriscv core
I encountered the error with misaligned memory access.
**To Reproduce**
Steps to reproduce the behavi…
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I have got an error when making ExampleRocketSystem as top.
![Example RocketSystem](https://user-images.githubusercontent.com/54856325/97796770-102c0a00-1c38-11eb-8c69-6a5a22bd1ea3.png)
The error is…
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I am having integer overflow error because of the large 256MB size of DRAM.
![issue ram](https://user-images.githubusercontent.com/54856325/97521342-32672300-19bf-11eb-9d84-7421edd031db.jpg)
I want…
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failing in travis.ci
pre-req is fixissue 65 to get tests running
progress so far fixing is that the litex stuff is being installed outside of the symbiflow-examples directory so a cd needs to ha…
scted updated
3 years ago
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I prepared a basic setup for running a Row Hammer attack using EtherBone to fill/check the memory and a simple DMA reader module. I did several tests on the Arty A7 board but was not able to induce an…
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I am finding the LiteX memory test runs extremely slowly - about 1 # per 5 minutes. Originally I thought it was hung as per https://github.com/enjoy-digital/litex/issues/609, but after investigating f…
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Hi,
Thanks for the great project.
I just build the top.bit from examples/xc7/linux_litex_demo with pre-gen files.
And I tried Ethernet boot with the setup from [LiteX wiki](https://github.com/e…
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I have a Lite+Debug VexRiscV based SoC on an Arty that is failing to get past the memory test.
GDB says:
```
(gdb) step
Note: CPU is currently in a trap: Illegal instruction 0x0000500f at 0x0000…
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```
$ python3 examples/sram_soc.py --baudrate=9600 nmigen_boards.arty_a7.ArtyA7Platform
make: Entering directory '/devel/HDL/src/lambdasoc/env/lib/python3.8/site-packages/lambdasoc-0.1.dev25+g7381b4…
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Hi,all
I'm use command `make upload PROGRAM=hello BOARD=freedom-e300-arty` in the `freedon-e-sdk `directory. so,you can tell me the why?
![111](https://user-images.githubusercontent.com/26727603…