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Hi i am new to Linux and working on to generate bitstream file for a Verilog file using Symbiflow for a Artix-7 FPGA. I successfully installed Conda in tool chain installation and moved to second part…
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Standalone TF example "Micro speech" compiled for the board will have no real use case. There is a need for feeding the example with audio data, taking outputs from the TF model and visualizing them o…
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Hi,
I just came across a bug that causes nMigen to report the wrong number of pins when the direction of the pins is set to bidirectional.
Test code:
```python
from nmigen import *
from nmige…
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I apologize in advance if this is the wrong place to post this, but I could not think of anywhere else. I intend to use the Zero-Riscy core as part of a Xilinx Vivado project, but I have encountered t…
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First, thanks for doing this all. Second, I have verified that your core really returns 2 for a "1+1" command issued in micropython "natively" on a Power9 Talos II running Fedora 30 for ppc64le as hos…
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Recently I tried running vexriscv SMP with 4 cores on arty a7 35t. But I was greeted with failed memtest. I did git bisect to narrow down which commit has broken 4 core implementation, and unfortunate…
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Right now each platform must define a `toolchain_program` function which will know how to program the device. The issue is there are tons of ways of programming a device. I propose that we teach nmige…
FFY00 updated
4 years ago
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I am having trouble flashing the Linux image to the Arty A7 35T.
`./make.py --board=arty --build` seems to run without a hitch. Warnings, but no showstoppers.
Relevant logs:
https://gist.github…
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**Problem:**
older Arty board flash needs dummy cycles of 11 while newer Arty boards need dummy cycles of 7.
**Question:**
what is the best way to solve this? create different board classes?
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Hello,
I'm afraid of frequent questions...
When I followed the explanation below URL, but I saw a build error. (I'm evaluating VexRiscv commit ddc59bc.)
- https://github.com/SpinalHDL/VexRis…