-
I think it's a great idea to split the buildenv from the firmwares.
The problem now, though, is that I have to have files in the platform, target, and firmware directories specific to a given appl…
-
Hello,
Chipyard support rocket with NVDLA, but this project only support VCU118. I want to implement this rocket with NVDLA project on other FPGA prototyping paltform. Which means I can't use Xilinx …
-
# Make floating point arithmetic optional in the Pascal-P machine
## The current state
Currently all floating point operations are allowed.
## The desired result
In order to allow for smal…
-
I've just bought the NETV2 from crowdsupply in it's quick start enclosure. The output port is constantly flashing and the input port does not flash at all. It does not seem to matter whether I have hd…
-
Right now, large CSRs spread across multiple "simple CSRs" whose size is ***NOT*** a multiple of 4 bytes are distributed in a counter-intuitive way. For example, a 17 byte CSR whose hardware value is:…
-
Hi,
I tried to load and run Bootrom, BBL and Linux Kernel on FPGA.
Bootrom and BBL can print on UART console without any issue, but the Linux Kernel cannot, even it went pass through a few place…
-
Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …
-
Hi
I can use VectorBlox-SDK to generate ultralytics.yolov5m.relu.vnnx correctly,but my device can't read ultralytics.yolov5m.relu.vnnx
![3](https://github.com/user-attachments/assets/7d661ba4-5b44-4…
-
Looks like JTAG boundary scan fails to find the ARM core on Kasli SoC.
* Kasli-SOC v1.1.1
* Ubuntu 2022.04 LTS
* Ubuntu AppArmor disabled
* [Incremental build](https://m-labs.hk/artiq/manual/bu…
-
I implemented RISCV SoC on a Zcu102 fpga. I am trying to use openOCD and jtag-hs2 to download code to the board as instructed in the README. Does anyone know what could potentially cause this error an…