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In commenting on a PR with ternary statements, I noticed an OpenTitan practice that I find alarming: Setting variables to X in the case of unhandled defaults. This is also recommended in the style g…
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To better support other Verilog/SystemVerilog-based projects that use Verilator for simulation, it would be nice to have the following features:
1. Passing customized file list to Verilator (`-f` opt…
ptpan updated
5 years ago
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The following SystemVerilog code:
```verilog
module rom(input [N-1:0] addr, output [3:0] data);
parameter N = 4;
integer i;
logic [3:0] mem[(1
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Author Name: **Udi Finkelstein**
Original Redmine Issue: 1429 from https://www.veripool.org
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While looking for a way to trigger an error on invalid parameter combinations of a parammetriz…
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Hello,
I like simplicity of your [SV grammar](https://github.com/zachjs/sv2v/blob/master/src/Language/SystemVerilog/Parser/Parse.y)
Seeing from history, you probably building it on your own.
Do…
Nic30 updated
5 years ago
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Author Name: **Oleg Rodionov**
Original Redmine Message: 3087 from https://www.veripool.org
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In my vcs simulation model, for certain, simulation content, I see majority of simulation time…
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Hello,
I have been recently interested in using [Nim](https://nim-lang.org) as a foreign language to interface with SV.
In my experiments, it had turned out to be a much more pleasant language t…
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Author Name: **Wilson Snyder** (@wsnyder)
Original Redmine Issue: 1606 from https://www.veripool.org
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Implement the built-in string methods that are remaining:
- atobin, atohex, atoi, …
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Guys, I am trying to run my cocotb testbench with Icarus. I have like 6 verilog modules - all included in one top level module. I have prepared my test and the make file which when I try to execute, I…
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Hello,
First of all this is not an issue, but I did not know where to place a comment.
And second of all, thanks for opening the door from Python to Verilator simulation!
I am interested in Ver…
ycrad updated
5 years ago