-
when i run top.v in the afu_driver/verilog ,i found the ");" is extra in 21 line .When i delete it ,i can simulate it
in vivado succeffully.please check it.thank you
-
The modelsim installation comes with pre compiled libraries (e.g. ieee, std, vital2000, etc) and it can also contain other pre compiled libraries (in my case all xilinx libs).
I don't like to use `…
-
SNAP code: master fd3fd0f 2017-01-20 09:56:36 +0100
Vivado=2016.4, IES=15.10.s19, SIMULATOR=irun,
DDR_USED=TRUE
DIMMCARD=adku060_capi_1_1_release
DIMMTEST=dimm_test-admpcieku3-v3_0_0
ACTION_ROOT…
-
Simulation with ddr3 sdram model (based on the patched dimmtest model) fails with the error message:
`ERROR: File: /afs/vlsilab.boeblingen.ibm.com/proj/fpga/framework/cards/dimm_test-admpcieku3-v3_…
-
I'm writing a Vivado AXI4 master VHDL component. And to test it I'm using cocotb with amba.py driver to test AXI4.
I had this error when I simulated it :
```Python
Send raised exception: Write t…
-
Hello,
I'm trying to run the example tests, when I try to make it fails with a segmentation fault. I'm posting the command prompt output. Please take a look. Thank you
user@system:~/Cocotb/example…
-
Edit: I believe the issue is not related to Cocotb but solely to VPI implementation in GHDL. However, I had no time to write a demo app to prove it, so it's demonstrated with Cocotb.
When using VPI…
-
Hello guys
I was following your tutorial on how to compile the pulpino, and I got to the part of: "make vcompile"
Now the problem is that modelsim is not working on linux, and i have tried everyth…
ghost updated
7 years ago
-
This is an issue to collect various issues related to the current regexp-based VHDL parser which can be solved by introducing a more proper parser
- See #144
- See #74
-
1) Some minor changes in **hardware/Makefile** :
at section clean :
=> use **rm -r -f** instead of **rm -rf**
=> use **rm -f ./setup/*.log** instead of **rm -f ./*.log**
=> use **rm -f ./setup/*.…