-
I recently noticed a bug in the way `bsc` pretty-prints `let` and `letseq` statements. The easiest way to observe the bug is by calling the `bsv2bsc` utility on this program:
```bsv
module helloWo…
-
使用版本0.2.4
当前启用扩展:
![image](https://user-images.githubusercontent.com/24518018/176985689-1634d24c-f75e-4dfb-b4ac-ed6cfb152549.png)
扩展设置:
![image](https://user-images.githubusercontent.com/24518018/…
-
按了几个插件之后就突然不行了,现在将之前的无关插件都卸载了,也不行
qgzln updated
2 years ago
-
When I activate the plug-in, the "begin end" code block changes from multiple colors to only one color
![图片](https://user-images.githubusercontent.com/49726805/146116615-f3032b5a-362d-4733-84d0-e5aee…
-
微博内容精选
-
SiliconCompiler is an open-source Python-based build system for ASIC design tools.
## Several pipecleaner designs
For this project, we would like to build a variety of small but realistic digita…
-
I'm working through the Symbiflow examples and modifying some using VS Code with the "Verilog-HDL/SystemVerilog/Bluespec SystemVerilog" plugin. So far I've seen, it does a good job at highlighting syn…
-
不知道为什么input和output不能正常高亮
![image](https://user-images.githubusercontent.com/96377023/146674815-15173976-cab9-4f09-a408-97d609558c88.png)
我之前一直用的Verilog-HDL/SystemVerilog/Bluespec SystemVerilog插件,但…
-
FloatingPoint::mkFloatingPointDivider deadlocks when dividing zero by something. Looking at the code and the VCD file, it appears that `s1_stage` detects the zero and sets `out` to a valid value. `s…
wlott updated
2 years ago
-
Visualstudio marketplace is a great place to publish vs code extensions but [its use licence](https://github.com/microsoft/vscode/issues/31168) only allow it to be used with the non-free Visual Studio…