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it won't build on arm64
```
/opae-sdk-2.1.0-1/libraries/plugins/vfio/opae_vfio.c:664:2: error: implicit declaration of function ‘__builtin_cpu_init’; did you mean ‘__builtin_irint’? [-Werror=implici…
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Hi
Using this API to program the binary in the FPGA:
kubectl rsu program -f -n -d
The documentation doesn't specify the arguments clearly, so assume signed_RTL_image is the name of the .bin …
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Hi all,
The HWPE behavior between simulation and FPGA is different. I've tried it with pulp_soc v2.1.0, v3.0.0 and v3.0.1. They all show the same problematic behavior so far.
**INFO:** I'm using…
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# Frontend Integration for AMC (Accelerator Memory Compiler) - Matt Hofmann and Yixiao Du
## Background
Our research area is in accelerator design, HLS (high-level synthesis), and FPGA CAD tools i…
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Master issue to track OpenCL support.
@danzimm -- if you end up issuing some PRs, please mention this issue. Thanks :100: :+1:
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In my fork, I have added some functionality to CVA5. I have a significantly modified environment in which I test, so cannot simply issue pull-requests right now.
Is there interest in somehow getting …
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@drichmond @mjacobsen
https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/chnl_tester.v#L128 is only cheating the receiving part. This means **we are not actually using the actual data r…
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Hi @noelpedro,
I have a version of your HDL running on a ZCU102 with an fmcomms2/3 card.
I'm seeing some strange behavior where my correlation results all drop and then re-adjust. This causes t…
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Hi.
I saw your interesting projects on the Innova2 - and wanted to ask you:
Have you used the Innova2 FPGA to control the network chip's (ConnectX-5) ingress/egress packets?
I want to hack some…