KastnerRG riffa issues - Githubissues

KastnerRG / riffa

The RIFFA development repository

https://riffa.ucsd.edu

Other

737 stars 306 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

riffa.py ctype type error due to float type entered into fpga_send length argument

#65 dsdy120 opened 2 weeks ago
0
Fix compilation of Linux driver

#64 marzoul closed 4 weeks ago
0
fpga_send loop error

#63 xlyzzz opened 3 months ago
0
AC701 Sample Code C_NUM_CHNL = 3 Channel 3 Receive 0

#62 FrankChuKontex closed 4 months ago
1
Fix driver for linux >= 6.5

#61 marzoul closed 9 months ago
0
riffa_driver.c: #elsif typo fixed

#60 erfanva closed 1 year ago
1
8+ fpgas

#59 werwolf opened 1 year ago
0
riffa on ubuntu

#58 erginatalar opened 1 year ago
10
A question about testutil.c

#57 emesjx opened 2 years ago
0
Executed ./testutil 0 command displaying 0 devices, but use lspci displaying Xilinx Corporation Device 7028, anybody know why?

#56 qingcai52 opened 3 years ago
1
UBUNTU20.0.4 failed to execute sudo make command

#55 qingcai52 closed 3 years ago
3
Build succes on Win10 but the resulting driver fails

#54 pmaBSA opened 3 years ago
0
Ubuntu 18.04 failed to compile

#53 robertstar closed 3 years ago
4
Fix for Windows handle leak

#52 cyealy opened 4 years ago
0
UBUNTU18.0.4 failed to compile and install

#51 vicmaaa closed 4 weeks ago
2
a big riffa bugs

#50 hushunkui opened 4 years ago
0
PCIe Gen2.0x16 or PCIe Gen3.0x16 support

#49 jixi2018 opened 4 years ago
1
RIFFA Virtex 6 series BAR memory area read write

#48 briansune opened 4 years ago
0
Riffa simulation

#47 jixi2018 opened 4 years ago
0
fpga_recv timeout

#46 bix010 opened 4 years ago
0
file include issue on functions.vh

#45 gxflying opened 4 years ago
0
riffa python example showed different data between TX and RX buffers

#44 jixi2018 opened 4 years ago
3
Cannot compile the driver on Ubuntu-18.04

#43 jixi2018 closed 4 years ago
5
I want riffa 2.1 for spartan6

#42 tanbakoo opened 4 years ago
0
PCIe x1 gen 2

#41 CedricDly opened 5 years ago
0
ERROR: [VRFC 10-1775] range must be bounded by constant expressions

#40 YiSyuanChen opened 5 years ago
3
calculation of config_link_rate is off for VC709

#39 hmaarrfk opened 5 years ago
0
wSchedule throws warnings for not being set in Vivado 2018.3

#38 hmaarrfk opened 5 years ago
6
Update sampleapp.py

#37 arkhodamoradi opened 5 years ago
0
Fix clog2s

#36 hmaarrfk opened 5 years ago
0
Why are the first four received words not as expected?

#35 Johnhave opened 5 years ago
1
Bulk data from PC to FPGA with slow user logic

#34 quangdaovu opened 5 years ago
1
riffa——learn

#33 moptutu opened 5 years ago
0
unable to resolve clog2s?

#32 Jzone315 opened 5 years ago
2
Added full duplex capability

#31 buttercutter opened 5 years ago
1
chnl_tester state machine flow issue

#30 buttercutter opened 6 years ago
8
Bandwidth drops for linux

#29 buttercutter opened 6 years ago
13
verilator testbench support

#28 buttercutter opened 6 years ago
0
root scope declaration is not allowed in verilog 95/2K mode

#27 buttercutter opened 6 years ago
5
Linux Driver Compilation Errors

#26 buttercutter closed 6 years ago
9
Virtex5 ml505 boards support

#25 skoroneos opened 6 years ago
0
Computer simply does not boot up

#24 Adrizcorp opened 6 years ago
0
Cannot compile in linux

#23 NotZombieFood closed 6 years ago
2
Windows Handle Leak in fpga_recv()

#22 mpernambuco opened 6 years ago
0
riffa: BAR 0 incorrect length

#21 loiron opened 6 years ago
3
Orientation questions about the project

#20 Piedone opened 6 years ago
4
fix #9 compile success in jetson TK1

#19 HongshiTan opened 7 years ago
2
Fix driver for linux >= 4.8

#18 marzoul closed 1 year ago
7
Fixes an initialization race condition

#17 jhicks-camgian opened 7 years ago
0
Jerry Hicks

#16 jhicks-camgian opened 7 years ago
2