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This is an feedback from @olofk.
![image](https://user-images.githubusercontent.com/2922232/210678769-4edf98e4-7ae4-4011-a459-091fa3413b5f.png)
* FuseSoC
* https://github.com/olofk/fusesoc
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similar to https://github.com/olofk/serv/issues/83 in WSL, the Windows version of `fusesoc` seems to not properly detect which version of python to use.
Here in Windows, `python` is Python versio…
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As discussed in #47, it would be nice to have fusesoc variants of the notebooks that show how to orchestrate openlane along other tasks like simulation and HDL generation.
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[edalize](https://github.com/olofk/edalize) is probably the most popular library for interfacing to EDA tooling and [used by the FuseSoC tooling](https://fusesoc.readthedocs.io/en/rtd/tutorials/1-gett…
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Currently `ci-fusesoc-action` uses container based action (https://docs.github.com/en/actions/creating-actions/creating-a-docker-container-action) to run `fusesoc` which makes easy to pull in fusesoc …
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As noted in https://github.com/olofk/serv/issues/83 I had some problems installing fusesoc in WSL due to a default python version issue.
I next tried to use Windows. I don't have Verilator installe…
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When running `make env` from the root directory everything passes fine. Later if any of CMake scripts gets modified and a command `make ` is invoked CMake tires to re-generate related Makefiles. Then …
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The Yosys flow in `syn` currently ingests source files from the rtl directory and other places, feeds them through sv2v, and then passes them through yosys.
Since https://github.com/lowRISC/ibex/pu…
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Would allow for much better portability and integration in to a higher level design. Allows for interface wrappers.
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**$ fusesoc run --target=sim swervolf**
INFO: Preparing ::cdc_utils:0.1
INFO: Downloading fusesoc/cdc_utils from github
INFO: Preparing chipsalliance.org:cores:SweRV_EH1:1.8
INFO: Downloading chip…