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After using the xtension successfully yesterday, today was slightly different.
![image](https://github.com/jainpranav1/Nand2Tetris-HDL-Visualizer/assets/157003150/75135e9b-5680-452b-b635-4ed1c31453…
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Hi Koide,
I have error in comment roslaunch hdl_graph_slam hdl_graph_slam_400.launch,
RLException: [hdl_graph_slam_400.launch] is neither a launch file in package [hdl_graph_slam] nor is [hdl_grap…
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1. roslaunch hdl_graph_slam hdl_graph_slam_501.launch
![fff](https://user-images.githubusercontent.com/7031071/155454721-f0d68e1c-4ad5-4d75-9986-a7c98115d033.png)
Please tell me how to fix the…
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### Summary 💡
Currently in the languages section a circle using the "chip" color is printed along the programming language name, it would be more attractive to the eye to have the colored **logo** …
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Hi!
Do you have any opinion about LIO-SAM (https://github.com/TixiaoShan/LIO-SAM) and its derivatives?
For example this paper: https://www.researchgate.net/publication/362466555_Evaluation_and_c…
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Hi @koide3,
Thanks for your hard wok. I run hdl with `use_global_localization = true, specify_init_pose = false`, then in the terminal `rosservice call /relocalize`, hdl can not be initialized with …
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Would it be possible to have rust-hdl output to circt. https://circt.llvm.org/
One could then use the LLVM/MLIR to optimize the output before outputting System Verilog or VHDL.
For example rust is …
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### Description
A vcs time profile for chip_sw_pwrmgr_smoketest shows 50% of the time is spent in uvm_hdl_deposit for mem_bkdr_util::write. This is excessive, and we should be able to reduce it signi…
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Qorivva CPUs mix sar and sigmal delta adcs, probably for onboard Knock control.
Investigation is required in availability of ADC devices in automotive temp grades that aren't too expensive but cove…
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PWM for outputs needs to be a completetly CPU free operation so it's all done in a pwm core