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HI!
I ran hls_model.build() and hls4ml.report.read_vivado_report('my-hls-test')
However after 5-10 mins, i got the output as Synthesis report not found. Co-simulation report not found.
- I ran t…
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## Issue Description ##
When trying to run the testbench for the example [rfnoc module](https://github.com/EttusResearch/uhd/tree/master/host/examples/rfnoc-example), it was configured fo…
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At first I must say your open-source FPU is really helpful for me, and I learn lots of knowledge about how to design FPU from it.
I find that in ```fpnew_pipe_out.sv``` you just add some registers …
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Hello there, folks
I've just cloned the XRT tree and built it on Ubuntu 20.04.1 LTS. I've got a SmartSSD from Samsung (based on the Kintex Ultrascale+, according to the docs). Everything worked lik…
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- The system is Ubuntu 16.04.
- The fpga is kintex ultrascale+ KU115.
- Using xshell remote link to the workstation.
when using lspci, I can detect the device.
```shell
$ lspci | grep Xi
04:…
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@cjbe @WeiDaZhang and I have been looking at the timing stability of DRTIO on Kasli (all comments apply equally to Sayma of course).
Expectation:
E1. The latency between TTLs on Kasli DRTIO slaves…
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There have been various discussions around the DI/OT FMC carrier in #56, but it seems for the time being like there is not a consensus yet. I am wondering what people think about the idea of developi…
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_From @hartytp on [2017-08-16 05:24](https://github.com/sinara-hw/sinara/issues/253)_
I've started sketching out requirements for a fast DAC to be used for ion shuttling/splitting. It's on the [Wiki…
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I have been having a look at the performance of Artiq on Zynq SOCs (2x ARM CPU + Artix/Kintex fabric). I am particularly interested in:
* the level of friction / mess in porting to Zynq
* the potent…
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Hi, do you have any plan to add the ultrascale-plus Kintex FPGA in example design? such as KCU116.