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Hi,
I have implemented **Rocket64b1gem16** on my FPGA with **default configs** and **8GiB DDR3**.
The ONNX Resnet18 Model sometimes can run with command '-O 99' and I can get the right result. But s…
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Hi,
I am a starter in this code and would like to initially change some Naxriscv instructions.
To provide some context, I was able to successfully compile and run litex, flash the board, and e…
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VPR is routing some designs on artix200t through unknown GTP PIPs.
In those designs, the GTP tiles carry the horizontal clocks to the BUFHCE primitives. Since the interconnect points are "real" and …
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Here's the patch I've applied to litex (latest upstream version, incl. all dependencies). Also shown are the commands I'm using to (attempt to) pull data out of the SoC with `litescope_cli`:
```dif…
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What is observed:
* A compiled litex bitfile for CMOD A7 35t using symbiflow toolchain does not work
* LED chaser does not blink the LEDs
* logging in via lxterm is not possible
* On the o…
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Hello! Thanks for your repositories first! I have a board=xc7k325tffg900-2(as the same as BOARD=kc705). However, it is RGMII for the ethernet on my board. (I have deleted the ethernet and then success…
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Hello,
I'm using the Broadcom® B50610 triple-speed PHY chip, and I'd like the FPGA run as MAC controller to communicate with the PHY chip.
I was wondering whether verilog-ethernet supports this …
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Hello I am a student using chipyard v1.10.0 for my thesis.
I am using a modified rocket-core branched from version [rocket-chip @ 47f7b71](https://github.com/chipsalliance/rocket-chip/tree/47f7b71…
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With the latest database from conda, the daisho-usb3 design fails in symbiflow with the following error:
```
prjxray.fasm_assembler.FasmInconsistentBits: FASM line "CMT_TOP_R_UPPER_T_X8Y200.PLL_CL…
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Hello,
I am trying to implement a cva6 on a Nexys A7 board. When I load the image on the board and try to load the demo through UART the program get stuck after this output
```
__ _ __ _ _m
…