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Hello,
When I am trying to run UVM tests, using the below command to generate riscv_arithmetic_basic_test for example:
make instr_gen_run SIMULATOR=questa TEST=riscv_arithmetic_basic_test ISS=sp…
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# RISC-V from scratch 4: Creating a function prologue for our UART driver (2 / 3)
A post continuing implementation of an NS16550A UART driver in RISC-V assembly. Function prologues are explained in …
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While trying to use Half-precision Floating point operations for riscv-v extension instruction set architecture with spike. My assembly code is giving me an error "An illegal instruction was execu…
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This was requested by users, the monolithic way in which we generate the RiscV machine is a bit odd.
Our riscv implementation looks like
```
machine RiscV {
// implementation of riscv archi…
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https://riscv.org/about/
https://en.wikipedia.org/wiki/RISC-V
**Description:**
RISC-V is a relatively new open standard instruction set architecture (ISA). With only 40 base instructions it is …
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Currently in the GCC compile we are running without any optimizations when we are compiling are test.
Will note that we are adding the optimization level -O3 only in the linker and the final compilat…
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For getting started with Spike it would be useful to have binary releases of PK under https://github.com/riscv/riscv-pk/releases.
Usecase: One already has the RISC-V Binutils and Spike installed. W…
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Hello, I have generated few tests(riscv_arithmetic_basic_test, riscv_jump_stress_test and riscv_mmu_stress_test), and observed that there is lot of repetition in generated instructions(means there are…
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Most `function clause execute` stanzas use a syntax like:
```
function clause execute (ADDIW(imm, rs1, rd)) = {
let result : xlenbits = sign_extend(imm) + X(rs1);
X(rd) = sign_extend(result[31…
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After increasing a number of instructions for ml target in the commit 2b2abda6fa0fdd35435cca615861fe3145996b14 the successful generation of a assembly code is only possible when generation timeout is…