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I want to modify your code so that it could take hls::stream& instead of hls::stream&
i.e from
void canny_edge_detection(stream& axis_in, stream& axis_out,
uint8_t& hist_hthr, uint8_t& hist_lth…
3togo updated
5 years ago
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1. Le nombre de :
- jte coupe la parole
- je dis "moi et..."
- "faut voir.... c'est pas simple...."
- les sluuuurps pendant les repas
2. Les citations improbables : avec un système de notation …
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https://github.com/OPCFoundation/UA-Nodeset.git
Mentioned by @AndreasHeine
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*Issue migrated from trac ticket # 5827*
**component:** organization | **priority:** trivial | **keywords:** industrial applications
#### 2022-06-20 08:12:47: carsten.born@vitronic.com created the i…
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We seem to have a driver installed correctly. It is a read-only axi dma.
_[ 976.113508] axidma: loading out-of-tree module taints kernel.
[ 976.120585] axidma: axidma_dma.c: axidma_dma_init: 71…
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Hi Brandon,
I tried to register a callback function for the RX channel using the axidma_set_callback() function. I modified the benchmark example for that reason, but unfortunately, the callback fu…
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The design does not currently meet timing due to an intra clock failure within the axi_mem_intercon core. Adding registers to the Slave interfaces should solve this issue. This was already done in the…
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I am currently using Ubuntu 22.04, however I have tested this on the Ubuntu 20.04.3 image and I get the same result.
In the [mipi_to_displayport.ipynb](https://github.com/Xilinx/Kria-PYNQ/blob/main…
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Hi, I am new to fpga based design and I am trying to do this tutorial and understand it. But it is not working on my system. I have errors 1 error in block design and 6 in implementation.
Block d…
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I'm trying to recreate the base overlay for Kria-Pynq.
I've got Vivado 2020.2.2 (Windows), which is the only version that should work (as I read [here](https://github.com/Xilinx/Kria-PYNQ/issues/19…