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I'm getting confised by the usage of your parser. After populating yy_verilog_source_tree using the provided functions described on https://codedocs.xyz/ben-marshall/verilog-parser/group__parser-api.h…
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When using the verilog file:
```
module __a__a(
input wire clk,
output wire [31:0] out
);
// ===== Pipe stage 0:
wire [31:0] p0_literal_1_comb;
assign p0_literal_1_comb = 32'h0000_00…
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This is a bit of an open-ended request to somehow incorporate indexing of the standard UVM library so that projects that use it can link to an authoritative source of information. The UVM library rar…
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module test_module_A (
**import common_pkg::*;**
sig_A_01,
sig_A_02
);
input sig_A_01;
output sig_A_02;
endmodule
++++++++++++++++++++++++++++++
module test_wrapper_AB (/*AUTOARG*/);
…
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Hi @danielholanda,
Your project was really great and it helped me a lot. I have successfully generated Verilog code as well as successfully creating a Quartus project. However, when synthesizing usin…
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记录NPC的简易调试器开发过程
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The original issue I brought up several years ago was that AUTOINST would sometimes include bit slices for ports that were signed and cause tools like DC to give warnings about signed to unsigned conv…
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I am curious on your thoughts in allowing pyVHDLModel to be used in analyzing partial (missing files) or mixed language projects. Currently, the Analyze function in `__init__.py` will raise an excepti…
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Please delete or fill out each section as appropriate:
---
## Issue Description
Current version requires BISON 3.0.4 or above (defined in CMakefiles.txt). However, it does not build under BIS…
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I encountered the following error while simulating with Vivado, it seems that some files are missing.
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Run…