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The style guide currently recommends the following style for case statements
```systemverilog
alway_comb begin
unique case(in[3:0])
4'b0001: out = 4'hE;
4'b0110: out = 4'hA;
4'b1…
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### Description
There doesn't appear to be any documentation of the various defines.
This is what I've been able to reverse-engineer.
Could you please review & correct where wrong, and please tel…
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I've recently hit a problem where Questa was segfaulting when running a simulation with System Verilog code. After providing a testcase to Mentor they've said the issue is down to the new optimisatio…
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This is a summary of the discussion at the Hurricane-2 debrief meeting.
Clock muxes and clock division registers should have first-class support in Firrtl. Not sure if this needs an accompanying C…
ben-k updated
5 years ago
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**main.sh**
```
iverilog -g2012 -gspecify \
-s testbench \
-D 'DUMP_FILE_NAME="./output/inverter.vcd"' \
-D 'SDF_FILE_NAME="./output/inverter.sdf"' \
-o ./output/iverilog_simulation_program
e…
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Some visualization tools like the one in Model Sim allow you to get a trace on what conditions triggered the signal's change. How hard would it be to modify Verilator so that I could ask it what line(…
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Hello,
I am using CMake as my build system for RTL simulations.
Very often I have a scenario where I have a custom command that would generate Verilog files.
I am using custom_commands rather tha…
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Hello Nunobrum,
I am not sure if this is the right place for a request like these so apologies in advance if this is the wrong place.
I have been very much enjoying running Qspice in batch modes…
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This issue is a discussion thread and followup about adding Chisel support to TerosHDL extension.
Here I list the initial points I identify as requirement for support:
- Chisel is a DSL based on…
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I have used benchmark_sweep/counter8 task with k6_frac_N10_tileable_40nm architecture. Full testbench successfully runs and give expected results. However, within same task I also generate preconfigur…