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### [EDIT] Summary:
* Non-blocking (`
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We want a structured way to write unit tests for the sim.v files (and a way to run them).
We want the unit tests to be compatible with at a minimum;
* Yosys
* Verilator
* Icarus Verilog
Bu…
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The installation layout under `$PREFIX/lib` is a bit crowded and strange:
```
$ ls result/lib
Bluesim exec Libraries SAT tcllib Verilog Verilog.Quartus Verilog.Vivado VPI
```
This doe…
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[Reference]()
- This lab was very well written and documented, I was able to follow what was being taught relatively well. The biggest thing that I think would help with this would be to implement …
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/)
### Feature…
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**Is your feature request related to a problem? Please describe.**
Customizing the Verilog Code Editor with different themes.
On changing themes of the simulator,
the theme for the Verilog code ed…
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Check whether or not following tools support generated CSR modules/RAL packages.
* Simulation
* Cadence Xcelium
* VHDL output
* Mentor Questa/ModelSim
* Aldec Riviera-PRO
…
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I have been using cocotb for a while and decided to switch to the Python runner approach instead of using a Makefile.
The problem that I found is that, when I use Xcelium as a simulator and open th…
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Spinal version: v1.10.1
Simulation tool: Synopsys VCS 2018
Here's the simulation code:
```scala
SimTimeout(500 ms)
val perpPort = dut.socInst.logicMainInst.coreInst.io.d_perp
…
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When we used Iverilog for the synthesis process, we encountered an abnormal error problem. Our `Subsystem.sv` file motivates its file `Subsystem_tb.sv` to fail to compile and test through Iverilog. We…