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I like the idea of an abstract project model. I have difficulties understanding the concept of how designs and file sets are to be used in the project model and what the difference between a design an…
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Creating a Clarifai workflow that embodies the concept you've described would involve a series of steps that capture the essence of your idea. While I can't directly create a Clarifai workflow in this…
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The GitHub action needs to open NEWS.md and update the file to indicate the new version number of {ss3sim} and the version number of SS3 being used.
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# Problem Definition
Currently, the Github action is only set up for notifying the gap analysis repo: https://github.com/RapidSilicon/Gap-Analysis
However, for RTL benchmarks, CI is need to certif…
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I've started creating some [Bazel build rules](https://github.com/rickwebiii/bazel_fpga_rules) to create an out-of-the-box command line Clash to bitstream synthesis toolchain. You give these rules a l…
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A couple of days ago, @antonblanchard tweeted:
> https://twitter.com/antonblanchard/status/1218733857735725057
> If you've always wanted to blink an LED using VHDL and all Open Source tools, wait …
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The no est and with est jobs could be combined, with an argument to tell which version to use.
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Hi everybody,
I tried to make transfer learning from the [stylegan2_config-f_lsun-car_384x512](https://github.com/open-mmlab/mmgeneration/tree/master/configs/styleganv2/stylegan2_c2_lsun-car_384x51…
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**HELP wanted**: I'd like to kindly ask anyone to test the current v1.05 branch (here be dragons).
Various exciting reviewed PR's have been merged into the [rc/1.05 branch](https://github.com/milky…
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If I use `iverilog -g2012 -S` to compile the following:
```
module test(input a, output reg b);
always @(*) begin
$display("foo");
b = a;
end
endmodule
```
What I …