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The bitfiles that we supply doesnt seem to work on the Opal kelly XEM6010-LX150 board.
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Fresh clone throws the following warings on `build env`:
```
CMake Warning at xc7/make/vivado.cmake:39 (message):
Vivado targets for dram_test_64x1d_vivado not emitted, XRAY_VIVADO_SETTINGS
…
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Hello, I am a newbie for 1G-CML.
I am now following the getting started guide and I've passed the loopback test (Actually, it is also doubtable).
However, my NIC cannot exchange any packets with o…
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# [SymbiFlow #10] Add support for Spartan 6 parts
More technical details at [SymbiFlow Idea #10](https://github.com/SymbiFlow/ideas/issues/10)
# Brief explanation
Spartan 6 is a hugely popula…
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For users who have license for these because they purchased an fpga from the vendor, and don't necessarily have access to vcs
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After executing the C.JR at cycle 12, with the contents of rs1=8, shouldn't the next rvfi_pc_rdata at cycle 15 be 8, and not just ignore the branch and increment to 4?
![c jr](https://user-images.…
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I work with a xilinx FPGA (spartan 6), with the ise toolchain, when i try to run the lab002 from fpga_101 i have an xst problem: ERROR: Xst: 2927 - "/home/hyde/Digital/Soc/fpga_101/lab002/build/top.pr…
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Idea for icon in readme:
https://giphy.com/stickers/Dreamforce-dream-force-astro-WjfaoYXUwFViqbK66M
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In some tests for some modules loopy seems to drop the Ethernet connection, either after one transfer or before any transfer has occurred. To check for the cause of these drops and bug fix (ensure rel…
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When running the testbench given, i get this output:
> Finished circuit initialization process.
at 2095010 ns: Note: Starting Read 1 at byte_counter=81 (/testbench_sd_spi/).
at 4862790 ns: Note:…