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Hi everyone!
I am using an xcku035 FPGA, which is not listed in the following link:
https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2024.1/Xilinx_Official_Platforms
Is this going …
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1. [Install XRT prerequisites] can clobber a Ubuntu 22.04 LTS installation since it `pip install pybind11` instead of install the OS's pybind11-dev. See https://github.com/Xilinx/XRT/issues/8109
2. […
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I am facing this error while launching the docker images
Error response from daemon: pull access denied for xilinx/vitis-ai-tensorflow2-gpu, repository does not exist or may require 'docker login': d…
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**Environment**
- OS: Ubuntu 20.04.5 LTS
- Vitis version: 2021.1
- Platform: [xilinx_u280_xdma_201920_3]
- TAPA version: 0.0.20220807.1
![estimated_resources](https:/…
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We are getting the following error when running software emulation ``` make emu ``` with Xilinx Vivado and Vitis - what could be the cause?
```
***************************************************
P…
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Trying to build project but getting errors
Vitis 2022.1
Ubuntu 22.04
u50 platform - xilinx_u50_gen3x16_xdma_5_202210_1
Steps to reproduce -
1. git clone https://github.com/fpgasystems/Vitis…
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I want to Download and unzip [mpsoc common system](https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-zynqmp-common-v2022.1.tar.gz) & [zcu102 base platform](https://www.xilinx.com/m…
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I am having a trouble in generating the bitstream file xclbin from the exported RTL file I did from Vitis HLS, I am using the command prompt executing this 'v++ -l --platform /home/centos/aws-fpga/Vit…
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I tried building the project on the new `vitis_2022_1` branch targeting U280, and it resulted in the following error on `make all`:
```shell
$ make all TARGET=hw DEVICE=/opt/xilinx/platforms/xil…
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I have been trying to carry out IP generation for vision-related examples, while I have been able to carry out synthesis there is an issue that I am facing during co-simuation.
I am using Vitis HLS…