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Sorry about this, I don't have any other way to contact you. I'm trying to write the firmware in SDK for the PS in a similar design based on your HLS code. I configured the DMA as SG and I am using t…
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Hello. Please and thank you in advance. I am trying to get this project working on my shiny new zybo, and I'm having trouble right out of the gate. Vivado is telling me that I'm missing a lot of IP…
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On which board this code is targeted.........?
ultrascale zynq or only zynq..........?
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Hi,
I am facing a problem when i build vector addition application project. I can build with Emulation-SW, but when I tried to build with Emulation-HW or Hardware. I got the error:
ERROR: [v\+\+ …
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Could this project add Xilinx Virtual Cable Support? JTAG and programming are very solid in this project, found some other XVC project, like https://github.com/kholia/xvcpi and https://github.com/Berk…
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elodg updated
6 years ago
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I looked at this project since I'm trying to optimize a RAM - to - reseved RAM transfer on a 7 series Zynq device.
It looks you did really a great work! It's explained very clearly and seem easy to u…
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Hello, I installed Vivado 2020.2 on a new machine, and tried to get the PMOD AD5 working by following [these instructions](https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips…
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I stumbled upon an interesting bug. Linux is unable to boot if the memory size is above 512mb. In litex BIOS the whole ram passes the tests and its working but as linux start to boot it cant boot if I…
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* [x] Prepare release branch
* [x] Check clean Git History
* If not, clean-up history by rebasing
* [x] Run coverage simulations locally -> Check 100% coverage
* [x] Test tutorial builds
* [x…