-
On operating system GNU/Linux x86-64
my_config.vhdl is configured with the following lines:
```
constant MY_BOARD : string := "Custom";
constant MY_DEVICE : string := "xc7vx690t-2ffg1761";
```
m…
-
```
Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive 'FDPE_5' has unconnected output pin
WARNING:NgdBuild:486 - Attribute "INIT" is not allowed on symbol "ODDR" of type
"ODDR". Thi…
-
See https://travis-ci.org/timvideos/HDMI2USB-misoc-firmware/jobs/80203042
```
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line:
/hom…
-
---
Author Name: **Jonathon Donaldson**
Original Redmine Issue: 951 from https://www.veripool.org
Original Date: 2015-08-04
Original Assignee: Wilson Snyder (@wsnyder)
---
Taking a slice of an enu…
-
Update(7-marts-2016)
first working beta3 image online.
MK PR passed build tests.
ready for signoff.
https://drive.google.com/file/d/0BwyLvgyVIdi8WFBraENyZ0dQUXc/view?usp=sharing
https://drive.goog…
-
```
Right now the hardware is built by invoking the xilinx tools from scripts,
which is great for our automated system, but not as great for the student
wanting to build the hardware themselves.
We…
-
Hello,
I noticed that using multiple trays (e.g., one as panel and the other for reserving some space on the top of the screen), the "fullscreen" action doesn't work as expected: the window is expand…
-
When `TristateSignal`s are used as top-level ports the signal is not converted to an `inout` when the target is Verilog. This appears to work in VHDL but not in Verilog.
In addition PR #74 appeared…
-
Latest CLaSH 0.5 generates invalid VHDL, according to Xilinx ISE compiler:
```
Compiling vhdl file "/home/m/exp/fpga/vga/vhdl/Main/topEntity1_11.vhdl" in Library work.
Entity compiled.
ERROR:HDLPars…
-
Hey there,
I am trying to build core for atlys board, and I got this error:
WARN: File ../orpsoc-cores/systems/atlys/bench/orpsoc_tb.v does not exist
WARN: File ../orpsoc-cores/systems/atlys…