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Hey,
It seems you are missed including a file:
> libcxl.h:21:22: error: misc/cxl.h: No such file or directory
(More errors follow but presumably they would be fixed by the inclusion of this file.)
…
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Author Name: **Stefan Wallentowitz** (@wallento)
Original Redmine Issue: 919 from https://www.veripool.org
Original Date: 2015-05-13
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Hi Wilson,
attached please find my proposed patch f…
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I am not sure how to define in.
But in order to avoid ISE warning (Size mismatch) I am using this construct. It works their but gives error in iverilog.
Address_In
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I'm seeing some strange behavior that _seems_ to relate to using a variable indexed Vector of Bundles in the RHS of an assignment.
The example testbench highlights the problem:
``` scala
package va…
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Author Name: **Jonathon Donaldson**
Original Redmine Message: 1404 from https://www.veripool.org
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I have a simple video driver design written in SystemVerilog that I'm compiling with veri…
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I'm trying to synthesize with yosys Verilog code instantiating a standard BRAM template.
Yosys works fine until I've added the BRAM initialization.
The snippet of code creating problems is the followi…
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When issue #65 was implemented I didn't realise it was permissible to overload standard system tasks in a custom VPI library. Conforming simulators _should_ call the user-defined task instead of the …
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Author Name: **Jeremy Bennett** (@jeremybennett)
Original Redmine Issue: 696 from https://www.veripool.org
Original Date: 2013-11-07
Original Assignee: Wilson Snyder (@wsnyder)
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This is an …
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Author Name: **Yves Mathieu**
Original Redmine Issue: 633 from https://www.veripool.org
Original Date: 2013-03-13
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Operator overloading is supported by SystemVerilog standard (chap 11.11 i…
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Author Name: **Jason McMullan** (@ezrec)
Original Redmine Issue: 623 from https://www.veripool.org
Original Date: 2013-02-21
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In the following code snippets, while functionally identical, …