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I would like to use icestudio in class e.g. to demonstrate the simulation of logic gates. Ultimatively I would like to create logic tables with the students.
I found following two descriptions but …
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I have the following .v file:
```
module tritest(
output my_tri_out,
inout my_tri_inout,
input my_in0,
input my_in1
);
assign my_tri_out =…
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It would be useful if the README in the example directory explain what the behaviour of the example should be. I guess it should blink the LEDs on the top of the board, but am unsure as I do not get …
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## Steps to reproduce the issue
Yosys 0.9+932 (git sha1 fcce9401, clang 9.0.0 -fPIC -Os)
input : top.v
```
module top (
output PIN_21, PIN_22, PIN_23, PIN_24, USBPU,
input CLK, PIN…
BigET updated
4 years ago
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See the Yosys issue that I just filed:
https://github.com/YosysHQ/yosys/issues/511
```assign my_signal = 1'bz;``` results in an active low output driver.
All current examples are using this for…
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Hi,
I initially opened the issue in yosys (https://github.com/YosysHQ/yosys/issues/1675), but @eddiehung recommended me to open it here. See his comment [here](https://github.com/YosysHQ/yosys/issu…
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Not an issue as such, but due to the lack of a forum will post here.
I would like to run the clock much higher to see what the limit is to run swapforth at.
I tried to het a handle on this by impleme…
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Use apio 0.5.6, I get the error as seen in the image - if I use 0.4.1 however on the the BX at least all is good
![RS error](https://user-images.githubusercontent.com/60004943/101794339-c525d200-3ad4…
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Hello, when running
`apio verify --board icestick`
I get the following error.
iverilog -o hardware.out -D VCD_OUTPUT= -D NO_ICE40_DEFAULT_ASSIGNMENTS "C:\Users\jemo0\.apio\packages\tools-os…
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Hello,
I just tried accessing the board after loading the bin... and I get an empty screen.
```
~/DevForth/iceBoard/swapforth/j1a>PYTHONPATH=../shell:$PYTHONPATH python3 shell.py -h /dev/tty…