jamesbowman swapforth issues

jamesbowman / swapforth

Swapforth is a cross-platform ANS Forth

BSD 3-Clause "New" or "Revised" License

274 stars 55 forks source link

issues

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Data stack always empty

#87 arblake closed 5 months ago
1
Converting j1a to use ICEbreaker

#86 arblake closed 5 months ago
4
The changes needed to simulate j1b with new Python3 and Verilator used in Debian/testing

#85 wzab opened 6 months ago
0
Verilator fixes with pyenv python

#84 RGD2 closed 9 months ago
0
Unnable to connect.

#83 jemo07 opened 1 year ago
6
apio error, can find ram.v for j1a

#82 jemo07 opened 1 year ago
1
The localtest doesn't work with Verilator 5.xxx

#81 wzab opened 1 year ago
3
Suspicious code in cross.fs

#80 ElectronicRU opened 1 year ago
0
Strings on j1b

#79 cicamargoba opened 1 year ago
0
add initial J1b support for ULX3S board

#78 stuij opened 1 year ago
1
fix more array.tostring() removal issues in Python 3.9

#77 stuij opened 1 year ago
2
update Verilator-related files to compile on version 4.228

#76 stuij opened 1 year ago
1
Fix array.tostring for Python 3.9

#75 higaski closed 2 years ago
1
[Feature request] further documentation on the J1 core versions

#74 higaski opened 2 years ago
2
Modification needed to run the bootstrap in swapforth/j1b/verilator w…

#73 wzab closed 2 years ago
1
J1B does not compile with the newest Verilator 4.210 2021-07-07 rev v4.210-19-gde408a5e

#72 wzab opened 2 years ago
1
Modifications needed to build with the Verilator v4.038

#71 wzab closed 2 years ago
0
Can it use the irda ?

#70 kwccoin opened 3 years ago
1
Completed port to TinyFPGA-BX board complete with soft USB port.

#69 bmentink opened 4 years ago
1
Python Emulator Issues

#68 PythonLinks opened 4 years ago
0
Compilation of J1B with Verilator does not work in Linux/Debian. Small modification of j1b.v needed.

#67 wzab opened 5 years ago
0
Incorrect literal with base-switching prefix changes the base for numerical conversions.

#66 wzab opened 5 years ago
0
Initial port of j1b to Lattice ECP5 FPGA

#65 bmentink opened 5 years ago
0
fix the common include paths

#64 kei77 opened 5 years ago
0
"$10 $0004 io!" does not turn the led on

#63 kei77 opened 5 years ago
0
What's EASE_IO_TIMING for?

#61 redfast00 closed 5 years ago
3
unhelpful error message improved

#60 dimyme closed 4 years ago
0
nandland.com go board

#59 oystercatcher closed 6 years ago
7
Fix for uart.v

#58 igor-m opened 6 years ago
0
#flash and mkrom.py issue

#57 igor-m closed 6 years ago
0
ram.v for ice40UP5k

#56 igor-m closed 6 years ago
4
I have ported j1b to Artix-7 (cmod-A7 board and Arty)

#55 bmentink closed 6 years ago
4
j1b does not have "init" vector

#54 bmentink closed 6 years ago
1
PapilioDuo does not hold configuration in flash

#53 bmentink closed 6 years ago
1
Problem with PapilioDuo board

#52 bmentink closed 6 years ago
1
Fix#45-afonly+icepll+69Mhz -- for testing.

#51 RGD2 opened 7 years ago
1
Fix#45 afonly+icepll

#50 RGD2 opened 7 years ago
0
Fix#45 afonly

#49 RGD2 opened 7 years ago
0
Fix#45

#48 RGD2 closed 7 years ago
5
Feature Request: Support for the ICOBOARD

#47 bmentink closed 6 years ago
2
How do I interface this fifo

#46 bmentink closed 6 years ago
6
serial data corruption at 460800

#45 bmentink opened 7 years ago
38
Is this project dead .. or just sleeping

#44 bmentink closed 7 years ago
2
simulator (verilator) does not compile

#43 bmentink closed 6 years ago
8
j1a8k doesn't use all available ram

#42 bmentink opened 7 years ago
11
Issues with files in common and j1a

#41 bmentink opened 7 years ago
1
How to add new peripheral to the code

#40 bmentink closed 6 years ago
18
Ramping up the clock rate

#39 bmentink opened 7 years ago
7
shell.py issues on ArchLinux

#38 bmentink closed 6 years ago
2
j1a IO is broken (SEVERE)

#37 RGD2 closed 7 years ago
7