-
Xilinx web pack does come with a [free ethernet mac]( https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/axi_ethernetlite/v3_0/pg135-axi-ethernetlite.pdf). The mac suppor…
-
I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
-
I am trying the NexSys_Video_example
In file nexsysvideo_ddr3.v, you set
.DQ_BITS(8), //width of DQ
.BYTE_LANES(1), //number of DDR3 modules to be controlled
Does this mean Nex…
-
Hi all,
I have a Pmod DA4 chip and I'm using with the Pynq-Z1 board as a two channel custom function generator. As of now I'm using the base overlay provided by the Pynq project to access the PmodB…
-
Dear @btashton,
What are the IP cores should be added in Zybo Z7 platform which is already written in litex-boards( https://github.com/litex-hub/litex-boards)
Does generating the bitstream with…
-
I think I've encountered a bug that affects the pin mapping for the Basys3 board (part name xc7a35tcpg236-1). I've got a program that maps the 16 switches to a seven segment display but the behavior o…
-
When generating RISC-V RTL in WSL Ubuntu terminal, I got the following error messages:
$ make CONFIG=rocket64b2 BOARD=nexys-a7-100t vivado-tcl
...
`java.nio.file.FileSystemException: /mnt/g/vivado-…
-
Hi,
I want to run a OpenMP code on Spike. I believe I need a Linux on Spike in SMP mode. So, could someone please help me with how I can get it up running?
Thank you
-
So I am using WSL2 in Windows to have an Ubuntu install without having to deal with dual booting. This has posed certian challenges, such as getting USB devices (an Arty A7 board for example) passed t…
-
Hi, When usning SiFiveTools->Flash MCS file to Arty FPGA in Freedom studio,I encounterd error:Unsupported DTM verdion:14.
The detailed log:
2019-07-05 13:48:17.811000: Running Command: C:\Jason\sifi…