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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
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Repro:
```python3
from nmigen import *
from nmigen_boards.arty_a7 import ArtyA7_35Platform
# Resource("eth_clk50", 0, Pins("G18", dir="o"),
# Clock(50e6), Attrs(IOSTANDARD="LVCMOS33"…
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Hello,
I understand that Arty A7 is supported, I want to confirm if Arty S7 need something extra to work.
I follow the build instructions and when loading the gateware on Arty S7 I am getting the …
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I have set up the UART example with Arty A7 100 board and I observe the following:
When I send data to the USB descriptior as:
```
echo "AAAA" > /dev/ttyUSB3
```
In the minicom I can see
…
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## Observed Behavior
When I try to simulate the Arty A7-35 example in Vivado, I get an error message in elaborate.log:
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/top_art…
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I just tried if I can reproduce https://github.com/enjoy-digital/litex/pull/1259 on BlackParrot.
Unfortunately using BlackParrot and the Arty board the `demo.bin` gets stuck on lift-off even if `-flt…
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So I am using WSL2 in Windows to have an Ubuntu install without having to deal with dual booting. This has posed certian challenges, such as getting USB devices (an Arty A7 board for example) passed t…
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The job https://github.com/apache/nuttx/actions/runs/4993159615/jobs/8941973789?pr=9138#step:7:448 shows an error while refreshing the `arty_a7:netnsh` defconfig.
This very same error happens while…
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hello!
I'm having a problem implementing the core in vivado.
I have installed the riscv gnu toolchain and I am sure that it works ok, I modified the Makefile ($TOOLCHAINPREFIX).
I ran the makfil…
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你好，我按照《教你设计CPU-RISC-V处理器》一书18.3内容从github上下载工程，并按照书本过程编译，但是最终生成的system.bit和system.mcs并不在书本上所写的 artydevkit/obj/ 目录内而是在 hbirdkit/obj 目录下并且烧录进 digilent arty a7 板内连接串口也没有返回值，请问这是为什么？有什么解决办法吗？
谢谢