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```bash
git clone https://github.com/litex-hub/linux-on-litex-vexriscv
git clone http://github.com/buildroot/buildroot
cd buildroot
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_ve…
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This is a proposal for a new testers API, and supersedes issues #551 and #547. Nothing is currently set in stone, and feedback from the general Chisel community is desired. So please give it a read an…
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**Environment**
OS: Ubuntu 22.04
Python: 3.10
VSG: 3.15.0 installed via `pip`
**Describe the bug**
Given the below MWE I get the following errors:
```
========================================…
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There is a desire to have a generic stream abstraction in `nmigen.lib` which can be used / presented by the `nmigen-stdio` cores (among others). This issue exists to capture discussion around the desi…
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Hi,
The litexGen isn't a self contained runner, it need some argument and anditional scala file to generate.
For instance, https://github.com/litex-hub/pythondata-cpu-naxriscv/blob/m…
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- [x] #54
- [x] #55
- [x] #77
- [x] #80
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Hi,
Thanks for your efforts.
I wanted to run a simulation as mentioned in http://sergeykhbr.github.io/riscv_vhdl/verification_page.html#sim_tb_link and unable to find the mentioned testbench file …
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Hi, I am running the NVDLA small architecture on a FPGA.
I succeded at running almost all the flatbufs tests available in the UMD. I just have a problem with the loadable `NN_L0_1_small_fbuf` , which…
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Hey Guys,
I worked with hls4ml the past few months and now I finally wanted to deploy a model I transformed with hls4ml, but I dont really know how I have to initialize my IP core created with hls4…