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Hello TT-BUDA Maintainers/Team,
I'm working with the tt-buda project and have a couple of questions regarding its implementation. I reviewed the documentation and relevant modules but couldn't fin…
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We are interested in mostly using the DRAM-v part of DRAM. In running the `DRAM-setup.py prepare_databases` command with no special options (no KEGG), we see that the database is quite large - and the…
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Would this tester be pin compatible with MCM6665AL20 DRAM chips?
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brisck.cc and ncrisck.cc (and erisc?) should issue a write_barrier to sync the noc before completing and telling dispatcher that everything is done. not doing so is a race, for example, a kernel writ…
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Hi I am trying to run fastswap in DRAM mode, the process of installing patched kernel and loading modules was successful, but I got a crash when trying to run quicksort benchmark, the crash happens in…
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Hi, I'm trying to implement the Deep Recurrent Attention Model described in the paper http://arxiv.org/pdf/1412.7755v2.pdf to apply to image caption generation instead of image classification. I will …
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I just bought a brand new Sonoff NS Panel and tried to flash the nspanel.tft firmware (version 53) onto it. Unfortunately, I wasn't able to complete the display firmware update. I tried several attemp…
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Hey, i used the following command `python3 -m litex_boards.targets.sipeed_tang_primer_20k --build --dock lite` to build a litex soc and after running it the memory init failed.
the following logs w…
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Hi, I am trying to install the software as described in the `README`. But I run into the error below when running `make -j`:
```
/Users/rajathsalegame/rds/ramulator2/src/dram/impl/DDR4-VRR.cpp:…
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How can I simulate a channel with a single x8 DRAM?
I can simulate a channel with four or two DRAMs by changing the "nbrOfDevices" parameter in the memspec .json file AND simultaneously change the…