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![Uploading 1.png…]()
10:06:05 INFO 开始读取 {"流": "34020000001320000001/34020000001320000001", "id": 1, "类型": "HDLSubscriber", "ID": "127.0.0.1:35354", "轨道": "h264", "mode": 0}
10:06:0…
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AD9361
hardware:Zedboard + FMCOMMS3 + AD9361
software:vitis2021.1, No-OS 2021.1
I changed nothing in main.c but still failed. The Vitis Serial Terminal reported:
Calibration TIMEOUT (0x5E,…
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Hi,
I am trying to develop a Stomp-Ws client using WebsocketPP.
The client is working fine in Ubuntu but leaking memory in Tizen.
Unfortunately, Tizen 3.0 doesn't support valgrind so I am unabl…
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Hi,
What IPXACT xml tag is mapped to the hdl_path of a component? For example, I have an IPXACT file that one of its field supposed to have hdl_path, which is described in "pathSements" field, but …
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How can I synthesize this using Quartus Prime ( windows). I have tried Adding the project and Running the files , but all i get are analysis error
Note : files are added as it is in project.
for E…
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Out of interest, for referencing in papers, and for some light boasting, it would be nice to have a list of papers using xdem in the documentation! A short non-comprehensive list is:
- https://doi.…
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Hi, I am using Neovim 0.9.5 Release on a Macbook running Sonoma 14.4.1 and Brew.
I used Mason to install rust_hdl and have the following in a lua script that is being executed without any errors i…
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Hi
i have doubt that can i simulate complete design on modelsim?
regards
hyanki
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**Describe the enhancement**
Support using a login shell along with the container step syntax.
**Code Snippet**
```yml
# Produces an error
Action_String:
needs: Image
runs-on:…
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github.com/parallella/oh/sw
* __best practice of 20 years of chip design__
* __silicon proven building blocks__