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jhshi
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openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
http://openofdm.rtfd.io
Apache License 2.0
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解码部分代码逻辑问题
#30
joker1-m
opened
5 months ago
0
How to compile and simulate
#29
wjq110
opened
5 months ago
0
is there any other implementation of 802.11 ofdm decoder in verilog avaliable or corrected version of the current repo please provide a solution
#28
huddy211
opened
1 year ago
1
The included module openofdm_rx_pre_def.v is missing please provide a solution
#27
huddy211
opened
1 year ago
1
The included openofdm_rx_pre_def.v modules isn't om the repository
#26
yurivict
opened
1 year ago
1
Changes for openwifi coming release
#25
JiaoXianjun
closed
1 year ago
0
Fix reserved bit in SIG-HT header
#24
redfast00
closed
1 year ago
0
Reserved bit in 802.11n should be 1 (instead of 0)
#23
redfast00
opened
1 year ago
1
Simulation enviorment set up
#22
gyn
opened
1 year ago
0
Bump numpy from 1.11.2 to 1.22.0
#21
dependabot[bot]
closed
2 years ago
0
Bump numpy from 1.11.2 to 1.21.0
#20
dependabot[bot]
closed
2 years ago
1
Improvement for openwifi-1.3.0-wilsele
#19
JiaoXianjun
closed
2 years ago
0
openwifi receiver improvements 2021
#18
JiaoXianjun
closed
2 years ago
0
incorrect indexing in sync_long.v
#17
gchampin
closed
2 years ago
1
Out of range error in test.py with sample file
#16
andreaskuster
opened
2 years ago
5
Provide ht_sgi signal out (for openwifi 11n release)
#15
JiaoXianjun
closed
3 years ago
0
add necessary port as trigger for iq capture feature in openwifi
#14
JiaoXianjun
closed
3 years ago
0
Typo
#13
f380cedric
closed
3 years ago
0
output information for openwifi side channel feature
#12
JiaoXianjun
closed
3 years ago
0
The latest receiver optimization from openwifi project
#11
JiaoXianjun
closed
3 years ago
0
Correct typo
#10
redfast00
closed
3 years ago
0
fix the simulation input file format of dot11_tb.v
#9
JiaoXianjun
closed
4 years ago
0
add new gen FPGA (zynqmp ultra_scale) support from openwifi project
#8
JiaoXianjun
closed
4 years ago
0
Simulation of full HDL
#7
hyanki
opened
4 years ago
3
Is this available for the IQ data captured from USRP B210?
#6
p577665228
opened
4 years ago
1
openwifi bug-fix and improvement
#5
JiaoXianjun
closed
4 years ago
0
abs_i name
#4
Jiahua-Gong
opened
5 years ago
0
Simulation of power trigger module
#3
hyanki
closed
5 years ago
0
testing on USRP
#2
weiliu1011
opened
5 years ago
2
rotate.v has 9 clock delay
#1
jinsanko
opened
6 years ago
0