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tries to run a rule call coco_test but no recipe exists in the makefile.
changing the rule to 'all' starts the test, which then fails with missing file:
![image](https://user-images.githubusercont…
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https://github.com/RTimothyEdwards/magic/issues/262
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Hi,
I guess I'm using naively the tool by comparing two netlists: initial RTL and one file after synthesis targeting Xilinx and providing Xilinx gates as blackboxes.
Still when doing so, the tool ha…
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### Description
OpenLane is fairly deterministic on either macOS or Linux, i.e., the same inputs/design will broadly run into the same errors.
However, a design failing on macOS may succeed on Lin…
donn updated
4 months ago
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I am trying to view a Netlist prepared for Kicad and get the following error:
```
The nelist file 'wd/board.net' didn't contain any subcircuit
```
After looking at the code and the SPICE forma…
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"Excuse me, could I take a moment of your time? I would like to know if it's possible to use MacroRank to sort the benchmarks I need in order, and I hope to output the sorted sequence of macros. Is th…
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Hello, me & my team are currently working on a project that can be summarized into hardware kit powered by a simulator (so no real hardware in the background), so real-time simulation is a must for us…
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As I show below,how do you normalize the wirelength?Whether or not the function of plc.get_cost considerd area?
![image](https://user-images.githubusercontent.com/95022180/160971894-aa0b99ca-d195-406…
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Is there a pass to remove passthrough modules? I'm seeing 1-input muxes in the post-synthesis netlists, and while this technically isn't illegal it's causing warnings in tools and ideally, I'd like to…