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### Version
Yosys 0.24+10 (git sha1 69cbef966, gcc 12.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os)
### On which OS did this happ…
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The directory at https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu has;
- blackparrot
- cv32e40p
- lm32
- microwatt
- minerva
- mor1kx
- picorv32
- rocket
- serv…
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There are some (many?) places in CFU Playground that assume the CPU is VexRiscv. What if any work would need to be done to allow other Litex-supported CPUs (SERV, PicoRV32, corev*, etc) to be dropped…
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Hello friend, the solution you mentioned in FFT-implementation-in-RISCV-using-PCPI is where I am learning but encountered big problems. I sincerely ask for your help. Are you willing to share Complete…
ichxm updated
5 months ago
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In tutorial 2, https://github.com/drichmond/RISC-V-On-PYNQ/blob/master/notebooks/tutorial/2-Creating-A-Bitstream.ipynb for skipping steps it is mentioned for skipping step 1 "To skip the first step, P…
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Here is a good [question](https://discord.com/channels/1103723077814190092/1103728793245454488/1258374640070557717) from @TurboVega:
> "... does anyone know how (command line option, maybe) to get…
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If I perform the following steps, everything builds ok using trellis, and I get the BIOS prompt.
```
cd litex-boards/litex_boards/targets
./radiona_ulx3s.py --build --device=LFE5U-85F --cpu-type=ve…
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@stv0g
https://github.com/cliffordwolf/picorv32/commit/eb64df6c3e5184ee982bb57c8828b80c798ce1b6
in file sections.lds and firmware.c
```
#ifdef ICEBREAKER
# define MEM_TOTAL 0x20000 /* 128 K…
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I've seen beginners (both in FPGAs and wrt the FOSS toolchain) have an issue where their design is mysteriosly not working because they forgot `--package`, and I made that mistake myself too. I think …