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Hi,
I am creating this issue in reference to the PCB design of the double trouble board. I need to use this board in my research, and hence, I have submitted the development files (https://github.com…
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Hi,
I am trying to import CHaiDNN to a xfopencv demo with HDMI input named filter2d, and build CHaiDNN to a shared library. But the platform of filter2d is zcu102_es2_rv_ss, not zcu102.
When I build…
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Hi, I have a question about the CU utilization of the array partition (cpp_kernels) example. If the overall Avg latencies of normal kernel and partition kernel are 9.522 us and 3.540 us respectively, …
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- [x] FPGAの部屋を参考にUltra96のminimalなHWプラットフォーム作成(余計なものを消すために) Vivado
- [x] FPGAの部屋を参考 or Avnetのconfigを参考にSWプラットフォーム=sysrootを作成 Petalinux
- [x] Vitis-AI TRDのVitis GUIフロー(マジであってよかった、なかったら死んでた)を参考にVitis…
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There are no documents about the usage of `hcl.platform`, and I can only guess from the provided examples. However, when I run the `test_vivado_hls` function in [test_runtime_build.py](https://github.…
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In Linux 5.4, several members of `struct drm_driver` have been deprecated in favour of their counterparts in `struct drm_gem_object_funcs`. In 5.11, they have been removed. This causes the DKMS compil…
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Hello,
How to reproduce:
I took the code from the 2019.2 branch and compiled with a 2019.2 Vitis.
The problem was observed xilinx_u200_xdma_201830_2 platform, and with XRT 2020.1.
When changin…
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Hello,
How to reproduce:
I took the code from the latest branch and compiled it with a 2020.2 Vitis IDE.
The problem was observed xilinx_u200_xdma_201830_2 platform, and with XRT 2020.2.
The H…
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Hello,
When I was running the test code DATA_TRANSFER, I wanted to change the read file to another place and change the size of the read file. I found that the size created in the test example was:…
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hi, i wanna know is that possible to make xclbin file in vitis?
and how can i config files in vitis 2020.2.