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I have Yices 2.6.2 installed, and a fairly recent bulld of saw (2e4fc060). Here's an unexpected error from them:
sawscript> prove z3 {{ \ (x:Integer) y -> ((x*y) == 0) == (x==0 \/ y == 0) }}
…
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~~~~
ghci> import qualified Data.SBV.List as SList
ghci> import Data.SBV as SBV
ghci> prove (\xs -> sNot (SList.all id xs) .== SList.any sNot xs)
*** Exception:
*** Data.SBV: Unexpected non-succ…
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Problem:
corrupted smt2-file syntax
Test:
```
g(x, x) -> h(x, h(x, x))
```
Broken syntax in smt2 file:
```
(assert (>= t1 (* + t5 t4 ))
```
And there are other problems with the model…
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cvc5 is able to solve `seed.smt2` nearly instantly but cannot solve the even simpler `bug.smt2`.
```smt
$ cat seed.smt2
(set-logic ALL)
(declare-fun a () Real)
(declare-fun b () Real)
(declar…
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for this case ：
```
(declare-fun arr () (Array Int Int))
(assert (forall ((x Int)) (=> (and (>= x 0) (< x 100)) (>= (select arr x) 0))))
(check-sat)
cvc5 test.smt2
unknown
z3 test.smt2
sa…
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When verifying a Verilog design using `ebmc` with large bounds, it takes long time to complete the verification. However, if I output the SMT formulas and solve the formulas using `z3` command, it tak…
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Commit: 2c35a4fd262a7aa1cc3b953265d327de4eae9f8e
```
$ cvc5 -q --strings-exp unknown.smt2
unknown
$ cvc5 --force-logic=SNRA unknown.smt2
unknown
$ cvc5 --force-logic=QF_SNRA unknown.smt2
unkn…
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After building dependencies, I proceeded to build metaSMT. (cd $metaSMT/build; make). This gives me the following error. How to fix this issue? My compiler specs are also given below.
## Compiler Sp…
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### Version
Yosys 0.28+6 (git sha1 cee3cb31b, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
Verilog file:
```verilog
module top (res, offset);
…
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