-
from pathlib import Path
import numpy as np
import pytest
import torch
import torch.nn as nn
from hls4ml.converters import convert_from_pytorch_model
from hls4ml.utils.config import config_f…
-
I observed the following pedantic warnings when running the `golay-24-systematic` source code through a beta version of Oracle's **Parfait** source code analysis tool.
```
Pedantic: Loss of precisio…
-
A number of fuzzers (and associated minitests) work on Vivado 2017.2 but are broken on Vivado 2017.3. A quick analysis shows its related to MUXF8.
-
I've got [a branch adding support for Layer Normalization](https://github.com/rianbrooksflynn/hls4ml/tree/layernorm) using either Keras or PyTorch with the Vivado backend in `io_parallel` mode, and I'…
-
There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
5 months ago
-
### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
-
Eugene, thank for all your work with the vivado-riscv.
That is excellent work.
Hopefuly not a stupid question but my NexsysA7 shows up with 83MB of memory but we have DDR on that board.
Did I mak…
-
Hello!
I am a student currently learning FPGA as part of my coursework. Our instructor places a lot of emphasis on hands-on experiments, and we were assigned several labs from Xilinx's official web…
-
I'm requesting that the syntax for environment variables be treated the same way for both Windows and Linux variables so that a vhdl_ls.toml can be checked into version control along with a project an…
-
if using the cheby-generated AXI4-Lite interface in Vivado block design without a wrapper following issues arise:
* the naming of the interface does not follow usual scheme of `[MS]_AXI_NAME`, inst…